李靖
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Pre One:[14]. Jian Luo, Jing Li, et.al, A 0.9-V 12-bit 100-MS/s 14.6-fJ/Conversion-Step SAR ADC in 40-nm CMOS,IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,pp.1980-1988, 2018.10.
Next One:Jian Luo, Jing Li, et.al, The Effects of Comparator Dynamic Capacitor Mismatch in SAR ADC and Correction,IEEE Access,pp.7037-7043,2018,06.
Release time:2021-04-15