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University of Electronic Science and Technology of China

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李靖

Personal information

Professor Supervisor of Doctorate Candidates
Name (Simplified Chinese):李靖
Name (Pinyin):lijing
Education Level:With Certificate of Graduation for Doctorate Study
Gender:Male
Degree:Doctor of Engineering
Status:Professor

Current position: Home >> Scientific Research >> Paper Publications

[21] Jing Li, Ning Ning, Ling Du, Qi Yu, and Yang Liu. The impact of gate leakage current on PLL in 65 nm technology: analysis and optimization[J]. Journal of Semiconductor Technology and Science, 2012, 12(1):99-105
[22] Jing Li, Yang Liu, Shuangyi Wu, Ning Ning, Qi Yu. Digital background calibration for timing skew in time-interleaved ADC[J]. Journal of Circuits, Systems, and Computers, 2014, 23(8):1450117(1-13)
[23] Jing Li, Yang Liu, Shuangyi Wu, Chang Yang, Ning Ning, Qi Yu. Design of a fast locking DLL with background timing skew calibration[J]. Nanoscience and Nanotechnology Letters, 2014, 6(12):1068-1074
[24] Jing Li, Ning Ning, Yong Hu, Kejun Wu. A Low-jitter Low-area PLL with Process-independent Bandwidth[C]. 2012 IEEE International Conference on Solid-State and Integrated Circuit Technology, Xi’an, 2012, 1-3
[25] Jing Li, Yang Liu, Shuangyi Wu, Ning Ning, Qi Yu. A background jitter optimization method for PLL based on time-to-digital converter[C]. 2014 IEEE International Conference on Electron Devices and Solid-State Circuits, Chengdu, 2014

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