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A Run-Time RTL Debugging Methodology for FPGA-based Co-Simulation

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Note:The 8th IEEE International Conference on Communications, Circuits and Systems (ICCCAS2010), July, 2010.

All the Authors:et al, A.W. Ruan,X. Cheng

Translation or Not:no

Pre One:An Automatic Test Approach for Field Programmable Gate Array (FPGA)

Next One:A New Event Driven Testbench Synthesis Engine for FPGA Emulation

阮爱武

Gender:Female Education Level:With Certificate of Graduation for Doctorate Study Degree:Doctor of Engineering Status:Professor E-Mail:

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