Release time:2019-08-08

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Affiliation of Author(s):UESTC

Teaching and Research Group:CRFICS

Journal:IEEE Journal of Solid-State Circuits

Key Words:Capacitors , Complexity theory , Noise shaping , Energy resolution , Robustness , Sun , Circuit stab

Indexed by:Applied Research

Volume:54

Issue:2

Page Number:428-440

Translation or Not:no

This paper presents a compact and power efficient third-order continuous-time (CT) delta-sigma (ΔΣ) analog-to-digital converter (ADC) with a single operational transconductance amplifier (OTA). A 4-bit second-order fully passive noise-shaping (NS) successive-approximation-register (SAR) ADC is employed as the quantizer while inherently provides two additional NS orders. Fabricated in 40-nm CMOS, the prototype occupies 0.029 mm 2 of active area and consumes 1.16 mW of power when clocked at 500-MHz sampling frequency. The proposed CT ΔΣ ADC achieves a peak signal-to-noise-and-distortion ratio (S